This invention relates to the field of semiconductor design. More specifically, the present invention relates to a method and apparatus for design verification.
Semiconductor fabrication processes include an initial design phase in which the circuitry is designed. Final layout assembly and verification is then performed for each new design. Only after the verification process has been successfully completed, can the semiconductor device fabrication process begin.
The complexity of semiconductor devices has risen exponentially in recent years, primarily as a result of increases in the number of transistors packaged on each semiconductor device. This has resulted in a corresponding increase in the development cycle. In particular, this increased complexity has significantly increased the time required to perform final layout assembly and verification for each new design. This stretches the development cycle and escalates verification run-times that are essential to ensure zero defects prior to fabrication.
Prior art verification cycles typically include numerous error correction and verification runs on the entire integrated chip. Because of the extensive amount of time required for each verification run, prior art processes for final layout assembly and verification of a very complex chip can take as long as twenty days to complete.
However, market forces dictate that semiconductor developers bring products quickly to market. This creates a need to shorten the time required to bring each new design of a semiconductor device to market and hence, a need to shorten the error correction and verification cycle.
In response to the need to shorten the verification cycle, various software programs have been developed for speeding up the error correction and verification process. These recent software programs have significantly decreased the run time for software verification. However, because of the continuing increase in the complexity of semiconductor designs, the sheer volume and complexity of data overwhelms many of the software programs that have been developed for speeding up the error correction and verification process, resulting in long run-times.
The use of faster microprocessors has also resulted in improvements to run time. In addition, programs have been recently introduced that run on multiple microprocessors. However, the use of fast microprocessors and the use of multiple fast microprocessors is expensive. In addition, as the complexity of semiconductor designs continues to increase, the processing power of multiple fast microprocessors may not be enough to maintain sufficiently fast run-times.
One step in the verification process includes the determination of the maximum spacing within or around a layer. This step is typically referred to as an electrical-distance check. Electrical-distance checks in physical verification (latchup) require large run-times and memory. Conventional tools for performing an electrical-distance check grow seed shapes using a repetitive iteration until the size of the seed shape reaches a limit, commonly referred to as the maximum distance. The process can be either inside or outside a shape set of interest. Each sizing is limited to avoid crossing the space or the notch of a barrier. At each iteration, the seed shapes represent the complete area that has been traversed during the growth.
FIG. 1 shows an exemplary conventional art electrical-distance check growth iteration that includes shape 102 and shape 103. In the example of Conventional Art FIG. 1, seed shape 104 and seed shape 105 are grown through N iterations until sizing Sn is reached. At iteration 5 the growth reaches the size of the smaller shape 102. However, in conventional processes, growth continues until iteration Sn. At iteration Sn, an error condition is reached as a result of the boundaries of shape 103 exceeding the sizing. An error report is then generated that indicates the portion of shape 103 not meeting the electrical distance check criteria. In this process, each iteration represents the complete area traversed.
Though the growth of the seed shape such that the seed shape represents the complete area that has been traversed during the growth gives accurate results, it requires the processing of a large amount of data. In addition, small barrier shapes, once fully traversed, wastefully participate in remaining cycles though they can grow no further. More particularly, in the example of Conventional Art FIG. 1, all growths within shape 102 following iteration 5, wastefully participate in future growth (e.g., iteration 6 through iteration N).
Thus, what is needed is a method and apparatus for bounded sizing of shapes that can efficiently determine sizing of shapes for verification of a semiconductor device design. In addition, a method and apparatus is needed that performs an electrical distance check quickly and accurately. In addition, a method for verification of semiconductor device design is needed that meets the above needs and that is not overwhelmed by the sheer volume and complexity of data that is required to be processed.
The present invention provides a method and apparatus for verification of a semiconductor device design that quickly and accurately processes data. In addition, the method and apparatus of the present invention is not overwhelmed by the sheer volume and complexity of data that is required to be processed.
A method and apparatus for verification of a semiconductor device design is disclosed that includes the determination of electrical distance for shapes within a design of a semiconductor device. In the present embodiment, the method includes growing each of a plurality of seeds to generate a first shape set that includes a plurality of shapes. Frontier edges are then determined for each shape within the first shape set. The frontier edges are then saved.
Each of the frontier edges are grown to generate a second shape set. Predetermined operations are performed on the second shape set to obtain frontier edges such that no frontier edges are determined for boundary shapes that have been fully traversed. The frontier edges are then saved. The first shape set is then replaced with the second shape set. The steps of growth of frontier edges to generate a second shape set; determining frontier edges; and saving frontier edges, is continued as long as the process produces at least one frontier edge or until growth has reached the electrical-distance to be tested for.
In another embodiment, frontier polygons are determined from the first shape set, and each frontier polygon is grown to generate a second shape set. Predetermined operations are performed on the second shape set to obtain frontier polygons such that no frontier polygons are determined for boundary shapes that have been fully traversed. The frontier polygons are then saved. The first shape set is then replaced with the second shape set. The steps of growth of frontier polygons to generate a second shape set; determining frontier polygons; and saving the determined frontier polygons, is continued as long as the process produces at least one frontier polygon or until growth has reached the electrical-distance to be tested for.
In the present embodiment, frontier edges are determined by dropping those portions of the edges of the shapes of the second shape set that overlap the shapes within the first shape set and dropping those portions of the edges of the shapes of the second shape set that extend beyond the boundaries of the shapes on which the electrical distance test is being performed. Similarly, frontier polygons are determined by dropping those portions of the shapes of the second shape set that overlap the shapes within the first shape set and dropping those portions of the shapes of the second shape set that extend beyond the boundaries of the shapes on which the electrical distance test is being performed.
Because the methods of the present invention track only the incremental growth, not the whole region flooded so far as in conventional methods, the present invention is much faster than conventional methods. In addition, the methods of the present invention do not require as much memory as do conventional methods. In addition, as each smaller shape is completely, or fully traversed, no frontier edges or frontier polygons result from subsequent growth steps. This advantageously reduces memory and run-time.
The method and apparatus of the present invention provides for efficiently determining bounded sizing of shapes for verification of a semiconductor device design, yielding shortened verification run-times. In addition, the method and apparatus of the present invention performs an electrical distance check quickly and accurately and is not overwhelmed by the sheer volume and complexity of data that is required to be processed.